The present invention relates generally to integrated circuit devices, and more specifically to high speed clocked memories having redundant arrays.
Redundant arrays are frequently used in memories to increase the overall yield above that which would normally be possible based on the random defect population density of a process. Random defect population density of a process may be caused by a number of factors, although particle defects, such as broken or shorted out rows, are the most normal cause of random process defects. Redundant row arrays, for example, are thus used to replace defective rows of the standard row array which are discovered during initial testing of the memory device. Redundant column arrays are similarly used to replace defective columns.
Continuing with the redundant row example, since it can not be known which row or rows of the standard row array may be defective, effective replacement of defective rows is accomplished using a redundant row array which may be programmed to replace any desired row of the standard row array. Programmability of the redundant row array is typically accomplished through the use of an electrical programming element, such as a laser fuse-link or anti-fuse, and a row decode tree. While this method provides the desired programmability, the result is, unfortunately, a redundant row array which is typically much slower than the normal row decode function.
This speed differential is especially of concern in high speed clocked memory devices where the overall memory access speed is often enhanced by pre-decoding much of the row addresses prior to the active clock edge during the address setup time. Thus, there is a current unmet need in the art to accomplish replacement of defective elements of the standard array with a redundant array in an efficient manner such that there is little or no speed differential between the normal decode function and the redundant decode function of the high speed clocked memory device.